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--- en:verilog:axis:readme [2014/11/09 10:27]
alex created
+++ en:verilog:axis:readme [2014/11/09 21:34] (current)
alex [Documentation]
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 ===== Documentation =====
+==== axis_adapter module ====
+The axis_adapter module bridges AXI stream busses of differing widths. The module is parametrizable, but there are certain restrictions. First, the bus word widths must be identical (e.g. one 8-bit lane and eight 8-bit lanes, but not one 16-bit lane and one 32-bit lane). Second, the bus widths must be related by an integer multiple (e.g. 2 words and 6 words, but not 4 words and 6 words). Wait states will be inserted on the wider bus side when necessary.
+==== axis_async_fifo module ====
+Basic word-based asynchronous FIFO with parametrizable data width and depth. Supports power of two depths only.
+==== axis_async_fifo_64 module ====
+Basic word-based asynchronous FIFO with tkeep signal and parametrizable data width and depth. Supports power of two depths only.
+==== axis_async_frame_fifo module ====
+Basic frame-based asynchronous FIFO with parametrizable data width and depth. Supports power of two depths only.
+==== axis_async_fifo_64 module ====
+Basic frame-based asynchronous FIFO with tkeep signal and parametrizable data width and depth. Supports power of two depths only.
+==== axis_fifo module ====
+Basic word-based synchronous FIFO with parametrizable data width and depth. Supports power of two depths only.
+==== axis_fifo_64 module ====
+Basic word-based synchronous FIFO with tkeep signal and parametrizable data width and depth. Supports power of two depths only.
+==== axis_frame_fifo module ====
+Basic frame-based synchronous FIFO with parametrizable data width and depth. Supports power of two depths only.
+==== axis_fifo_64 module ====
+Basic frame-based synchronous FIFO with tkeep signal and parametrizable data width and depth. Supports power of two depths only.
+==== axis_frame_join_N module ====
+Frame joiner with optional tag. 8 bit data path only.
+Can be generated with arbitrary port counts with axis_frame_join.py.
+==== axis_ll_bringe module ====
+AXI stream to LocalLink bridge.
+==== axis_rate_limit module ====
+Fractional rate limiter, supports word and frame modes. Inserts wait states to limit data rate to specified ratio. Frame mode inserts wait states at end of frames, word mode ignores frames and inserts wait states at any point. Parametrizable data width. Rate and mode are configurable at run time.
+==== axis_rate_limit_64 module ====
+Fractional rate limiter with tkeep signal, supports word and frame modes. Inserts wait states to limit data rate to specified ratio. Frame mode inserts wait states at end of frames, word mode ignores frames and inserts wait states at any point. Parametrizable data width. Rate and mode are configurable at run time.
+==== axis_register module ====
+Datapath register. Use to improve timing for long routes.
+==== axis_register_64 module ====
+Datapath register with tkeep signal. Use to improve timing for long routes.
+==== axis_stat_counter module ====
+Statistics counter module. Counts bytes and frames passing through monitored AXI stream interface. Trigger signal used to reset and dump counts out of AXI interface, along with tag value. Use with axis_frame_join_N to form a single monolithic frame from multiple monitored points with the same trigger.
+==== ll_axis_bridge module ====
+LocalLink to AXI stream bridge.
 ==== Common signals ====