Verilog Mersenne Twister PRNG

Mersenne Twister PRNG with an AXI4-Stream interface. Data can be read out on every cycle after seeding completes, resulting in 5.6 Gbps for the 32 bit version and 11.2 Gbps for the 64 bit version when running at 175 MHz. Includes both 32 bit (mt19937ar) and 64 bit (mt19937-64) synthesizable verilog implementations along with reference C and Python implementations. Includes full MyHDL testbench with intelligent bus cosimulation endpoints.

32 bit version on a Spartan 6: 175 MHz, 4 BRAMs, 226 FFs, 412 LUTs

64 bit version on a Spartan 6: 175 MHz, 4 BRAMs, 388 FFs, 829 LUTs

Verilog Mersenne Twister Readme

• Verilog Mersenne Twister on GitHub

• Icarus Verilog simulator
• MyHDL
• Mersenne Twister PRNG