====== Verilog UART ======

===== Introduction =====

I2C interface components.  Includes full MyHDL testbench with intelligent bus cosimulation endpoints.

===== Documentation =====

[[readme]]

===== Repository =====

  * [[http://github.com/alexforencich/verilog-i2c/|Verilog I2C on GitHub]]

===== Links =====

  * [[http://iverilog.icarus.com/|Icarus Verilog simulator]]
  * [[http://www.myhdl.org/|MyHDL]]